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Flip chip still in growth phase, even at $16B.

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[verwijderd] 13 april 2011 16:57

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Renewed interest in flip-chip technologies is motivated by the rising cost of gold used for wire bonding, the need for thinner devices, continued CMOS downscaling, higher currents and temperatures, and lower voltages.

Mobile applications are increasingly requiring footprint and weight reduction coupled with higher electrical performance (signal propagation and power distribution) that excludes wire bonded packages. The emergence of the 28nm CMOS technology node in particular poses new quality and reliability constraints on interconnect technologies, due to fragility, which may disqualify wire bonding. Increasing I/O density neccessitates new bumping and substrate technologies.

Flip-chip technologies and applications are diverse, with different drivers, levels of maturity, and sometimes alternative technologies. Flip-chip applies to a number of different applications addressing different packaging forms. To some, flip-chip applies to large digital system-on-chip (SOC) devices like microprocessors, graphical processor units or chipsets for personal computers and gaming stations. Flip-chip applies not only to packages but also to interconnection of bare integrated circuits, like the display drivers found around all LCD screens worldwide; and flip-chip packages can address devices with die sizes ranging from less than 1mm2 up to the maximum die sizes (around 650mm2).

The flip-chip market is undergoing major technology and supply chain transformations: emerging copper (Cu) pillar popularity, technology investments, changes to the supply chain, the role of CMOS foundries in flip chip packaging, and substrate cost/value

www.electroiq.com/index/display/packa...

(Besi with it's members Datacon, Fico and Meco is the leading manufacturer of flip chip and multi-chip die bonding, die sorting, packaging and plating equipment for both array connect and leadframe assembly applications. )

gaan we nog een paar leuke jaren tegenmoed volgens dit rapport.

[verwijderd] 20 april 2011 09:51

Copper pillars appear in packages from Amkor to Unisem, says Vardaman

April 14, 2011 -- E. Jan Vardaman, president and founder of TechSearch International, delivered a keynote address at the International Conference on Electronics Packaging (ICEP) held in Nara, Japan April 13-15. One of the key messages in her presentation was the trend toward the adoption of copper (Cu) pillar as highlighted in TechSearch International’s recent study, Flip Chip and WLP: Market Projections and New Developments.

Since Intel’s adoption of copper, many companies are moving to adopt copper pillar as the technology for their flip chip applications. Intel started with the use of copper pillar in its 65nm and 45nm flip chip product lines, and is using the technology in its 32nm products. The first products were the "Presler" and "Yonah" processors, but today Intel uses the copper pillar process in all of its flip chip products, including its Atom processor.

Cu pillar with a solder cap has also been used for GaAs and silicon in RF modules for several years. Amkor has been shipping RF Power Amplifier and RF front-end modules with Cu pillar bumps for more than four years. Drivers included size, performance, and cost.

Copper pillar is also shipping in leadframe packages from companies including Carsem and Unisem. IBM developed a copper pillar process called C2 that has been introduced for wire bond die with 50µm pitch or larger. TI has recently announced its use of Cu pillar in the bottom package of its package on package (PoP) offering.

Advantages of copper pillar, or copper post as it is sometimes called, were highlighted in TSMC’s recent technology day when TSMC presented its roadmap for the technology. Vardaman noted in her keynote that "the move to copper pillar is similar to the industry's progression from the evaporated bump to the plated bump, and a major shift is expected in the 2013-14 timeframe."

Highlighted in the ICEP presentation was STATS ChipPAC’s low-cost FC-CSP based on copper columns, bond-on-lead interconnection, and molded underfill. A 20-40% lower cost over standard flip chip packages for most designs has been reported. Several subcontract assembly operations offer molded underfill, including Amkor, ASE, and STATS ChipPAC.

The tremendous interest in copper pillar was evident at ICEP with a standing-room-only crowd listening to ASE’s presentation on its plans for Cu pillar in FC-CSPs.

dit zijn goede signalen voor Besi.....

[verwijderd] 19 mei 2011 11:14

STATS ChipPAC invests in copper wire bonding for 45nm, low-k

May 4, 2011 - Marketwire -- STATS ChipPAC Ltd. (SGX-ST: STATSChP), semiconductor test and advanced packaging service provider, has shipped over 300 million semiconductor packages with copper wire-bond interconnects. The SATS provider is investing in Cu wire bonding for finer silicon nodes (45/40nm) and low-k/extra low-k (ELK).

STATS ChipPAC is investing in equipment and resources to support copper wire technology in wafer nodes down to 45/40nm with low-k and ELK dielectric materials. Development work is focused on finer bond pad pitches, thinner wire diameters, stacked die packaging and die-to-die bonding, each of which represents a greater set of challenges in the application of copper wire.

The transition from gold to copper wire interconnect in semiconductor packages offers a significant savings in material costs while meeting electrical and thermal performance characteristics with quality and reliability standards that are comparable to gold wire, the company states. STATS ChipPAC has copper wirebond capabilities in all five of its manufacturing facilities in Asia, each with class 1000 cleanroom environments.

Production volume has been rapidly increasing in both leadframe and laminate packages. "We are in high-volume manufacturing for a large number of devices across multiple factories and have built significant momentum on the engineering front to introduce copper wire into a wider range of applications in the communication, computing and consumer markets," said Hal Lasky, EVP and chief sales officer, STATS ChipPAC.

"We are successfully addressing many of the technical challenges that are associated with using copper wire interconnect in more complex package structures. We have been aggressively developing copper wire capabilities in all our factories and rapidly expanding into a broader range of fine pitch devices and advanced silicon nodes. Our dedicated resources, especially our strong global copper wire engineering organization, ensure a consistent and successful transition to copper wirebond for our customers," said Dr. Han Byung Joon, EVP and chief technology officer, STATS ChipPAC.

"STATS ChipPAC is investing in equipment and resources" mooie regel...

[verwijderd] 20 mei 2011 11:45

...•We can already feel that some consolidation is ahead in the semiconductor equipment and material market

www.i-micronews.com/upload/Rapports/Y...

vandaar dat ook JPM een belang in Besi neemt...

[verwijderd] 15 maart 2013 11:19

Nu 2 jaar later,

Flip-Chip Market and Technology Trends

Cu pillar and µbumping for memory, consumer electronics and mobile phones have reinvigorated the Flip-Chip market, enabling it to grow at a 19% rate and cater to the most advanced technologies, like 3DIC and 2.5D

Over the next five years, an incredible 3x wafer growth is expected for the Flip-Chip platform, which will reach 40M+ of 12’’eq wspy by 2018!
Despite its high 19% CAGR, Flip-chip is not new -- in fact, it was first introduced by IBM over 30 years ago! As such, it would be easy to consider it an old, uninteresting, mature technology…but this is far from true! Instead, Flip-Chip is keeping up with the times and developing new bumping solutions to serve the most advanced technologies, like 3DIC and 2.5D. Indeed, no matter what packaging technology you're using, a bumping step is always required at the end!
In 2012, bumping technologies accounted for 81% of the total installed capacity in the middle-end area. That's big. Really big. So big that it represents 14M+ 12’’eq wafers (2012 installed capacity: see figure below) -- and fab loading rates are high as well, especially for the Cu pillar platform (88%). Flip-Chip is also big on value: in 2012 it was a $20B market (making it the biggest market in the middle-end area), and we expect it to continue growing at an 9% clip, ultimately reaching $35B by 2018!

Flip-Chip capacity is expected to grow over the next five years to meet large demand from three main areas:
1) CMOS 28nm IC, including new applications like APE and BB;
2) The next generation of DDR Memory;
3) 3DIC/2.5D Interposer using µbumping. Driven by these applications, Cu pillar is on its way to becoming the interconnect of choice for Flip-Chip.

In addition to traditional applications which have used Flip-Chip for a while now (laptop, desktop and their CPUs, GPUs & Chipsets -- which are growing slowly but still represent significant production volumes for Flip-Chip), we expect to see strong demand from Mobile & Wireless (smartphones), Consumer applications (tablets, smart TV, set top box), Computing and High-Performance/Industrial applications such as network, servers, data centers and HPC.
The new "Flip-Chip packaged ICs” are expected to radically alter the market landscape with new specific motivations that will drive demand for wafer bumping. In the context of 3D integration and the "More than Moore" approach, Flip-Chip is one of the key technology bricks and will help enable more sophisticated system on chip integration than ever before!
Flip-Chip is being reshaped by a new kind of demand that is hungry for Cu pillars and µbumps, which are on their way to becoming the new mainstream bumping metallurgy for die interconnection.

www.i-micronews.com/reports/Flip-Chip...

de trein gaat zo vertrekken.........instappen, ook de achterblijvers niet treuzelen!!!!

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